SPI (Serial Peripheral Interface)#
Overview#
- Synchronous, full-duplex serial bus.
- Master-slave architecture (1 master, multiple slaves).
- Uses 4 wires:
- SCLK (clock), MOSI (Master Out Slave In), MISO (Master In Slave Out), SS/CS (Slave Select).
Physical Layer#
- Push-pull outputs (faster than open-drain).
- Each slave requires a dedicated SS line.
Data Frame Structure#
- No start/stop bits – continuous stream synchronized to SCLK.
- Data sampled on clock edges defined by CPOL (clock polarity) and CPHA (clock phase):
- Mode 0: CPOL=0 (idle low), CPHA=0 (sample on rising edge).
- Mode 3: CPOL=1 (idle high), CPHA=1 (sample on falling edge).
SCLK | MOSI (Data from Master) | MISO (Data from Slave) | CS (Active Low)
Key Features#
- Full-duplex communication (simultaneous MOSI/MISO).
- No addressing – slaves selected via SS lines.
- Speeds: Up to 100+ Mbps (depends on hardware).
Pros & Cons#
| Pros | Cons |
|---|
| High-speed communication | High pin count (n+3 for n slaves) |
| Simple protocol, flexible modes | No built-in error detection |
| Full-duplex support | No multi-master support |
Use Cases#
- High-speed sensors (e.g., IMUs).
- Display controllers (OLED, TFT).
- SD cards, NOR flash memory.
Comparison Table#
| Feature | UART | I2C | SPI |
|---|
| Clock | None (async) | Shared (SCL) | Shared (SCLK) |
| Duplex | Full-duplex | Half-duplex | Full-duplex |
| Topology | Point-to-point | Multi-device | Master-slave |
| Speed | Low (≤115kbps) | Moderate (≤3.4Mbps) | High (≥10Mbps) |
| Addressing | None | 7/10-bit | Hardware (SS lines) |
| Pins | 2 (TX/RX) | 2 (SCL/SDA) | 4 + n (SS per slave) |
| Error Handling | Parity bit | ACK/NACK | None |